The speed at which integrated circuit components function has increased rapidly in the past several years. For example, today's processors now function at speeds greater than one gigahertz, a vast improvement over processors available only a few years ago. Improvements are likely to increase processing speeds even further in the near future.
Memory component manufacturers, in an attempt to compliment the faster processors, have decreased memory device access times. Access time refers to the amount of time needed to complete a read or write operation within the memory device. By decreasing access time, the throughput of a memory device (i.e., the amount of data transferred within a given period) can be increased. For example, synchronous dynamic random access memory (SDRAM) was designed to overcome limitations inherent in previous memory devices. SDRAM utilizes an external clocking signal to match the timing of the memory operations with the operations of the other components of the integrated circuit, thereby decreasing device latency and improving throughput.
Initially, SDRAM was contained within a memory card. The memory card was comprised of several memory arrays, which contained one or more memory banks. Each memory bank was further comprised of a multitude of individual memory cells, arranged in rows and columns, which contained the information stored within the SDRAM.
During a write operation, a processor issued commands to an appropriate memory controller. The commands included address information and control signals (such as read or write signals, among others) The memory controller decoded the address signals to produce a row address strobe (RAS) signal and a column address strobe (CAS) signal, among others. A multiplexer, connected to the memory controller, routed the RAS signal and the CAS signal to the correct memory array (or memory bank within an array). The RAS signal was received by a row address decoder, which activated the appropriate row within a memory bank. Likewise, the CAS signal was received by a column address decoder, which activated a sense amplifier connected to the appropriate column within the memory bank. Thus, the RAS and CAS signals were used to select and to activate an individual memory cell (or cells) within the memory bank. After the selected memory cell was activated, data was transferred from a data bus to the cell.
During a read operation, the processor issued commands to the appropriate memory controller. As discussed above in conjunction with the write operation, a RAS signal and a CAS signal were produced to select and to activate the memory cell (or cells) within the memory bank. After the row and column address decoders activated the selected memory cell (or cells), data was transferred from the cell to the data bus.
In most applications, the memory card was placed within a memory slot; connected to, but external to, the integrated circuit. A multitude of traces connected the memory slot, and hence the memory card, to the integrated circuit. The memory card contained contact pins to connect the memory controllers to the traces. Due to space limitations, however, the memory card contained a finite number of contact pins. Thus, to overcome the space limitations, several arrays within the memory card (or memory banks within the arrays) were multiplexed to share a common controller. With this architecture, only a single array (or bank) within the group of memory arrays (or banks) could be accessed at a given time by the shared controller.
Connecting the arrays (or banks) with a multiplexer necessitated the use of additional control signals, such as precharge and latch signals among others. A precharge signal was used to raise the voltage level of a bank's row (or column) before the row (or column) was accessed by a write or read operation. The precharge ensures that a state change will occur during the write or read operation which can be sensed by the memory array's sense amplifier. Application of a precharge signal decreased the memory device's throughput because another row (or column) could not be accessed until the precharge level was reached.
A latch signal “locks” the signal being sent to the memory bank, such as RAS and CAS signals for example, for a specified period of time. One purpose of the latch signal was to stabilize the memory bank while data was written to or retrieved from the memory cell. Again, throughput was decreased because a specific amount of time, usually governed by the physical characteristics of the memory bank, had to pass before a different signal (such as a command signal, address signal, data signal, etc.) could be applied or sensed.
The delays caused by the precharge and latch signals, among others, is called latency. For example, if a RAS signal is applied to select a specific row within a memory bank, the amount of time that must pass before another signal can be applied, such as a CAS signal, is called the RAS latency. Likewise, if a CAS signal is applied to select a specific column within a memory bank, the amount of time that must pass before another signal can be applied is called the CAS latency. The greater the latency, the smaller the throughput.
In addition to the inherent space limitations, externally mounted SDRAM suffered from propagation delays. Propagation delay refers to the additional amount of time required by a signal to travel through a trace, or electrical conductor, caused by the resistance, or impedance, of the trace. As a general rule, a signal traveling through a longer trace will have a greater propagational delay than a signal traveling through a shorter trace made from the same material. The traces between external memory cards and the integrated circuits are relatively long compared to other traces within the integrated circuit. Therefore, signals traveling between the external memory cards and the integrated circuit have greater propagational delays than other signals within the integrated circuit.
Manufactures have attempted to overcome some of the problems associated with externally mounted SDRAM by embedding the SDRAM directly within the integrated circuit. Such embedded technology is also referred to as a system in package (“SIP”) environment. For example, current embedded SDRAM has proven to be faster than external SDRAM because shorter traces can be used, thereby reducing the propagational delay. However, current embedded SDRAM technology continues to utilize multiplexed memory arrays (or banks). Thus, the current embedded SDRAM continues to suffer from throughput limitations inherent in multiplexed memory arrays (and banks).
Therefore, there exists a need for a device and a method that overcomes the throughput limitations inherent in external SDRAM. Furthermore, there exists a need to overcome the throughput limitations inherent in current embedded SDRAM.